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Computer Organization and Assembly Language

Computer Organization and Assembly Language

Introduction

Study the relationship between machine instructions, memory, processors and lower-level programming.

Topic-Wise Overview

Computer Systems

Compilation, processors, caches, storage hierarchy and operating systems

Data Representation

Binary information, integers, arithmetic and floating-point values

Machine-Level Programming

Instruction encodings, registers, procedures, arrays and pointers

Debugging and Security

Machine-level debugging, memory references and buffer overflow

Processor Design

Instruction-set architectures, hardware control and pipelining

Study Guidance

Study the complete collection of 200 Computer Organization and Assembly Language MCQs below, organized into four sets of 50. Every question has four options, a correct answer, and an explanation. Topics include computer systems, data representation, assembly instructions, CPU architecture, cache and virtual memory, pipelining, performance, input/output, storage, and machine-level security.

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Computer Organization and Assembly Language — MCQs 1–50

Select an answer and reveal its explanation.

Question 1. CPU purpose?

  1. Execute machine instructions
  2. Store all data permanently
  3. Operate Wi-Fi only
  4. Display images only
Show correct answer and explanation

Correct answer: A. Execute machine instructions

The processor executes machine code.

Question 2. ALU purpose?

  1. Disk storage
  2. Arithmetic and logical operations
  3. Network routing
  4. Operating system installation
Show correct answer and explanation

Correct answer: B. Arithmetic and logical operations

The ALU computes numeric and logic results.

Question 3. Control unit role?

  1. Archive documents
  2. Design websites
  3. Direct processor control signals
  4. Only calculate hashes
Show correct answer and explanation

Correct answer: C. Direct processor control signals

Control logic sequences execution.

Question 4. Register definition?

  1. Magnetic disk
  2. External monitor
  3. Network address
  4. Small fast CPU storage
Show correct answer and explanation

Correct answer: D. Small fast CPU storage

Registers hold processor operands and state.

Question 5. Program counter contains?

  1. Next instruction address
  2. Hard disk size
  3. Number of cores
  4. Operating-system name
Show correct answer and explanation

Correct answer: A. Next instruction address

The PC tracks the instruction stream.

Question 6. Instruction set architecture?

  1. Cooling fan arrangement
  2. Programmer-visible instructions and machine state
  3. Printer control software
  4. Only memory size
Show correct answer and explanation

Correct answer: B. Programmer-visible instructions and machine state

ISA defines machine-level operations and interfaces.

Question 7. Opcode field?

  1. Contains network domain
  2. Always specifies a file path
  3. Identifies an instruction operation
  4. Only stores user input
Show correct answer and explanation

Correct answer: C. Identifies an instruction operation

Opcode selects the operation.

Question 8. Operand means?

  1. A compiler error
  2. A hard drive
  3. Only a comment
  4. A value or location used by an instruction
Show correct answer and explanation

Correct answer: D. A value or location used by an instruction

Instructions operate on operands.

Question 9. Assembler performs?

  1. Assembly to machine-code translation
  2. Physical circuit design
  3. Wi-Fi configuration
  4. File compression
Show correct answer and explanation

Correct answer: A. Assembly to machine-code translation

The assembler encodes mnemonics into instructions.

Question 10. Compiler performs?

  1. Manufacture chips
  2. Translation of higher-level source programs
  3. Operate monitor pixels
  4. Only encrypt files
Show correct answer and explanation

Correct answer: B. Translation of higher-level source programs

Compilers generate lower-level representations.

Question 11. Linker role?

  1. Issue machine instructions
  2. Create raw data
  3. Combine object modules and resolve references
  4. Control cooling fans
Show correct answer and explanation

Correct answer: C. Combine object modules and resolve references

Linkers connect compiled modules.

Question 12. Loader role?

  1. Write original source
  2. Design a processor
  3. Only manage printing
  4. Prepare executable program memory for running
Show correct answer and explanation

Correct answer: D. Prepare executable program memory for running

Loaders map executable segments.

Question 13. Executable means?

  1. A loadable program artifact
  2. A memory cell
  3. A network cable
  4. A text comment only
Show correct answer and explanation

Correct answer: A. A loadable program artifact

Executable formats contain program code.

Question 14. Instruction cycle?

  1. Only backup and restore
  2. Fetch decode execute sequence
  3. Only input and output
  4. Only compile and link
Show correct answer and explanation

Correct answer: B. Fetch decode execute sequence

Processors process instructions through these stages.

Question 15. A bit is?

  1. Eight bytes
  2. A whole instruction always
  3. One binary digit
  4. An address bus
Show correct answer and explanation

Correct answer: C. One binary digit

A bit has value zero or one.

Question 16. Standard byte size?

  1. 4 bits
  2. 16 bits
  3. 32 bits
  4. 8 bits
Show correct answer and explanation

Correct answer: D. 8 bits

One byte has eight bits.

Question 17. Eight-bit unsigned pattern count?

  1. 256
  2. 255
  3. 128
  4. 512
Show correct answer and explanation

Correct answer: A. 256

Two to the eighth gives 256 patterns.

Question 18. Maximum unsigned eight-bit number?

  1. 256
  2. 255
  3. 127
  4. 128
Show correct answer and explanation

Correct answer: B. 255

Range is zero through 255.

Question 19. Decimal 13 in binary?

  1. 1011
  2. 1110
  3. 1101
  4. 1001
Show correct answer and explanation

Correct answer: C. 1101

Eight plus four plus one gives thirteen.

Question 20. Binary 1010 in decimal?

  1. 8
  2. 12
  3. 5
  4. 10
Show correct answer and explanation

Correct answer: D. 10

Eight plus two gives ten.

Question 21. Binary 1111 in hexadecimal?

  1. F
  2. E
  3. A
  4. 10
Show correct answer and explanation

Correct answer: A. F

Four ones represent fifteen.

Question 22. Hexadecimal A in decimal?

  1. 12
  2. 10
  3. 8
  4. 15
Show correct answer and explanation

Correct answer: B. 10

A denotes ten in base sixteen.

Question 23. One hexadecimal digit encodes?

  1. 2 bits
  2. 8 bits
  3. 4 bits
  4. 16 bits
Show correct answer and explanation

Correct answer: C. 4 bits

Sixteen combinations need four bits.

Question 24. 1100 AND 1010?

  1. 1110
  2. 0110
  3. 0010
  4. 1000
Show correct answer and explanation

Correct answer: D. 1000

Only the high bit is one in both.

Question 25. 1100 OR 1010?

  1. 1110
  2. 1000
  3. 0110
  4. 0000
Show correct answer and explanation

Correct answer: A. 1110

OR yields one where either input is one.

Question 26. 1100 XOR 1010?

  1. 1110
  2. 0110
  3. 1000
  4. 0010
Show correct answer and explanation

Correct answer: B. 0110

XOR is one for differing bits.

Question 27. Unsigned left shift by one without lost bits?

  1. Divide by two
  2. Invert every bit
  3. Multiply by two
  4. Add one
Show correct answer and explanation

Correct answer: C. Multiply by two

The place values double.

Question 28. Unsigned right shift by one?

  1. Multiply by two
  2. Add two
  3. Change every bit
  4. Floor divide by two
Show correct answer and explanation

Correct answer: D. Floor divide by two

Dropping the low bit halves the integer.

Question 29. Two’s complement represents?

  1. Signed integers
  2. File permissions
  3. Network addresses only
  4. Only floating point
Show correct answer and explanation

Correct answer: A. Signed integers

Two’s complement encodes signed integers.

Question 30. Signed eight-bit two’s complement range?

  1. Zero to 255
  2. Negative 128 to positive 127
  3. Negative 127 to 128
  4. Zero to 127
Show correct answer and explanation

Correct answer: B. Negative 128 to positive 127

The representable interval is asymmetric.

Question 31. Eight-bit negative one encoding?

  1. 00000001
  2. 10000000
  3. 11111111
  4. 01111111
Show correct answer and explanation

Correct answer: C. 11111111

All ones encode negative one in two’s complement.

Question 32. Sign extension does?

  1. Only append zeros always
  2. Multiply by two
  3. Sort bytes
  4. Preserve signed value when widening
Show correct answer and explanation

Correct answer: D. Preserve signed value when widening

Leading copies of the sign bit preserve value.

Question 33. Zero extension does?

  1. Add high-order zero bits
  2. Add high-order ones
  3. Invert each bit
  4. Add a checksum
Show correct answer and explanation

Correct answer: A. Add high-order zero bits

Zeros preserve the unsigned magnitude.

Question 34. Fixed-width overflow means?

  1. Every successful addition
  2. Result outside representable range
  3. A disk error
  4. Only a syntax error
Show correct answer and explanation

Correct answer: B. Result outside representable range

Finite bit widths limit numeric range.

Question 35. Common floating-point standard?

  1. ASCII
  2. UTF-8
  3. IEEE 754
  4. Ethernet
Show correct answer and explanation

Correct answer: C. IEEE 754

IEEE 754 specifies binary floating-point formats.

Question 36. Floating-point exponent controls?

  1. CPU core count
  2. Disk sector
  3. Cache replacement
  4. Numeric scale
Show correct answer and explanation

Correct answer: D. Numeric scale

Exponent scales the significand.

Question 37. Floating-point significand represents?

  1. Significant precision digits
  2. A network address
  3. Only program length
  4. A page table entry
Show correct answer and explanation

Correct answer: A. Significant precision digits

It carries the meaningful digits.

Question 38. Decimal one tenth in binary floating point?

  1. Always exact in binary32
  2. Usually cannot be represented exactly with finite bits
  3. Always an integer
  4. Requires no exponent
Show correct answer and explanation

Correct answer: B. Usually cannot be represented exactly with finite bits

One tenth has a repeating binary fraction.

Question 39. NaN means?

  1. Next Address Number
  2. New Arithmetic Notation
  3. Not a Number
  4. Network Access Node
Show correct answer and explanation

Correct answer: C. Not a Number

NaN is a special floating-point value.

Question 40. Endianness specifies?

  1. Instruction execution order
  2. CPU clock speed
  3. Number of registers
  4. Byte order of multibyte values
Show correct answer and explanation

Correct answer: D. Byte order of multibyte values

It defines memory byte arrangement.

Question 41. Little endian low address contains?

  1. Least significant byte
  2. Most significant byte
  3. Always zero
  4. Only sign bit
Show correct answer and explanation

Correct answer: A. Least significant byte

The least significant byte comes first.

Question 42. Big endian low address contains?

  1. Least significant byte
  2. Most significant byte
  3. Always zero
  4. Only exponent
Show correct answer and explanation

Correct answer: B. Most significant byte

The most significant byte comes first.

Question 43. Byte addressing means?

  1. Each address identifies a full disk
  2. Only instructions are addressed
  3. Each address identifies a byte
  4. No bytes can be accessed
Show correct answer and explanation

Correct answer: C. Each address identifies a byte

Byte-addressed memory indexes bytes.

Question 44. Alignment means?

  1. Values are sorted
  2. Data are encrypted
  3. Instruction is skipped
  4. Address respects required boundary
Show correct answer and explanation

Correct answer: D. Address respects required boundary

Aligned objects begin at suitable multiples.

Question 45. Size of a 32-bit quantity?

  1. 4 bytes
  2. 8 bytes
  3. 16 bytes
  4. 2 bytes
Show correct answer and explanation

Correct answer: A. 4 bytes

32 divided by eight equals four.

Question 46. Size of a 64-bit quantity?

  1. 4 bytes
  2. 8 bytes
  3. 16 bytes
  4. 64 bytes
Show correct answer and explanation

Correct answer: B. 8 bytes

64 divided by eight equals eight.

Question 47. RAM expansion?

  1. Read Arithmetic Machine
  2. Remote Access Module
  3. Random Access Memory
  4. Register Address Mode
Show correct answer and explanation

Correct answer: C. Random Access Memory

RAM denotes random-access memory.

Question 48. Volatile memory?

  1. Keeps data forever
  2. Only optical disk
  3. Only firmware
  4. Loses contents on power removal under normal operation
Show correct answer and explanation

Correct answer: D. Loses contents on power removal under normal operation

Ordinary RAM is volatile.

Question 49. ROM traditionally stores?

  1. Nonvolatile firmware or read-only data
  2. Only temporary stacks
  3. Only network packets
  4. CPU execution flags
Show correct answer and explanation

Correct answer: A. Nonvolatile firmware or read-only data

ROM is nonvolatile storage.

Question 50. Cache memory?

  1. Slow archival tape
  2. Fast storage of useful recently accessed data
  3. A network cable
  4. Only display memory
Show correct answer and explanation

Correct answer: B. Fast storage of useful recently accessed data

Caches exploit locality.

Computer Organization and Assembly Language MCQs — Questions 51–100

Choose an option and reveal the answer and explanation.

Question 51. Temporal locality?

  1. Nearby data are never used
  2. Every access is random
  3. Recent data may be reused soon
  4. All data are permanent
Show correct answer and explanation

Correct answer: C. Recent data may be reused soon

Caches exploit recent access patterns.

Question 52. Spatial locality?

  1. Only one register is used
  2. Every access repeats the same address
  3. All addresses are distant
  4. Nearby addresses may be used soon
Show correct answer and explanation

Correct answer: D. Nearby addresses may be used soon

Cache blocks exploit spatial locality.

Question 53. Cache hit?

  1. Requested block found in cache
  2. Cache is full necessarily
  3. A page fault always occurs
  4. Data were deleted
Show correct answer and explanation

Correct answer: A. Requested block found in cache

Hits use a fast storage level.

Question 54. Cache miss?

  1. CPU has stopped
  2. Requested block not present
  3. All data lost
  4. Only a network error
Show correct answer and explanation

Correct answer: B. Requested block not present

Misses fetch data from a lower level.

Question 55. Cache line?

  1. One opcode
  2. A CPU core
  3. A block of contiguous bytes stored in cache
  4. A disk directory
Show correct answer and explanation

Correct answer: C. A block of contiguous bytes stored in cache

Caches transfer blocks.

Question 56. Direct-mapped cache?

  1. Any line available
  2. No cache address
  3. Only random placement
  4. One possible cache line per memory block
Show correct answer and explanation

Correct answer: D. One possible cache line per memory block

Each block maps to one index.

Question 57. Fully associative cache?

  1. Any eligible cache line can hold a block
  2. Exactly one location for a block
  3. Only ROM data
  4. No tags
Show correct answer and explanation

Correct answer: A. Any eligible cache line can hold a block

Placement is unrestricted by fixed indexing.

Question 58. LRU replacement?

  1. Always evicts newest line
  2. Evicts least recently used line
  3. Deletes all data
  4. Uses only addresses
Show correct answer and explanation

Correct answer: B. Evicts least recently used line

LRU favors recent accesses.

Question 59. Write-through cache?

  1. Never writes data
  2. Always delays all writes until eviction
  3. Propagates writes to a lower level
  4. Only reads
Show correct answer and explanation

Correct answer: C. Propagates writes to a lower level

Backing storage is updated as part of the write policy.

Question 60. Write-back cache?

  1. Never records writes
  2. Requires write through each store
  3. Only caches instructions
  4. Defers lower-level updates for dirty lines
Show correct answer and explanation

Correct answer: D. Defers lower-level updates for dirty lines

Dirty lines may be written later.

Question 61. Virtual address?

  1. An address within a process virtual space
  2. Only a hard disk sector
  3. A network MAC address
  4. A physical CPU serial number
Show correct answer and explanation

Correct answer: A. An address within a process virtual space

Address translation maps virtual addresses.

Question 62. Page table?

  1. Records compiler warnings
  2. Records page mappings and permissions
  3. Stores monitor settings
  4. Stores only process names
Show correct answer and explanation

Correct answer: B. Records page mappings and permissions

Page tables support virtual memory.

Question 63. TLB?

  1. Temporary Loading Bus
  2. Terminal Logic Binary
  3. Translation Lookaside Buffer
  4. Transfer Link Buffer
Show correct answer and explanation

Correct answer: C. Translation Lookaside Buffer

A TLB caches translations.

Question 64. Page fault?

  1. Always a hardware defect
  2. A compiler error
  3. Every cache hit
  4. Access requiring virtual-memory fault handling
Show correct answer and explanation

Correct answer: D. Access requiring virtual-memory fault handling

Fault handlers can load pages or enforce access rights.

Question 65. Virtual memory benefit?

  1. Address-space abstraction and protection
  2. Unlimited physical memory
  3. No possible page faults
  4. Only image compression
Show correct answer and explanation

Correct answer: A. Address-space abstraction and protection

Virtual memory isolates process addresses.

Question 66. Stack organization?

  1. First in first out only
  2. Last in first out
  3. Random order
  4. Sorted order
Show correct answer and explanation

Correct answer: B. Last in first out

Recent pushes are popped first.

Question 67. Stack pointer?

  1. Tracks hard drive size
  2. Tracks network ports
  3. Tracks current stack position
  4. Stores only an opcode
Show correct answer and explanation

Correct answer: C. Tracks current stack position

SP denotes a stack boundary.

Question 68. Call instruction?

  1. Deletes code
  2. Resets the CPU
  3. Only initializes memory
  4. Transfers control to a subroutine and saves return information
Show correct answer and explanation

Correct answer: D. Transfers control to a subroutine and saves return information

Calls enable procedures.

Question 69. Return instruction?

  1. Resumes execution at a saved return point
  2. Always reboots
  3. Allocates physical RAM
  4. Only sets zero flag
Show correct answer and explanation

Correct answer: A. Resumes execution at a saved return point

Return restores caller flow.

Question 70. Stack frame?

  1. Only network packets
  2. Stores activation-related local and saved information
  3. Only user passwords
  4. Only disk sectors
Show correct answer and explanation

Correct answer: B. Stores activation-related local and saved information

Frames organize procedure data.

Question 71. MOV instruction?

  1. Multiply two integers only
  2. Always jump
  3. Move or copy data
  4. Stop processor
Show correct answer and explanation

Correct answer: C. Move or copy data

MOV transfers values between supported operands.

Question 72. ADD instruction?

  1. Perform bitwise NOT
  2. Always branch
  3. Read disk sector
  4. Perform addition
Show correct answer and explanation

Correct answer: D. Perform addition

ADD computes sums.

Question 73. SUB instruction?

  1. Perform subtraction
  2. Compute an OR operation
  3. Store a file
  4. Decode Unicode
Show correct answer and explanation

Correct answer: A. Perform subtraction

SUB computes a difference.

Question 74. CMP instruction?

  1. Copy all registers
  2. Compare operands and update status flags in common ISAs
  3. Always multiply values
  4. Stop all interrupts
Show correct answer and explanation

Correct answer: B. Compare operands and update status flags in common ISAs

Comparison often sets condition status.

Question 75. Unconditional jump?

  1. Only jumps when zero flag is set
  2. Always returns
  3. Transfers control without testing a condition
  4. Only reads memory
Show correct answer and explanation

Correct answer: C. Transfers control without testing a condition

Unconditional branches redirect execution.

Question 76. Conditional branch?

  1. Always transfers control
  2. Always clears memory
  3. Only executes on startup
  4. Uses condition flags or predicate to choose a target
Show correct answer and explanation

Correct answer: D. Uses condition flags or predicate to choose a target

Branches choose paths according to conditions.

Question 77. Zero flag?

  1. Indicates zero result of a relevant operation
  2. CPU is powered off
  3. All registers are cleared
  4. Disk is full
Show correct answer and explanation

Correct answer: A. Indicates zero result of a relevant operation

Zero status helps conditional branching.

Question 78. Carry flag?

  1. Only signed overflow
  2. Indicates carry or borrow conditions for unsigned arithmetic
  3. Network transmission loss
  4. Only page faults
Show correct answer and explanation

Correct answer: B. Indicates carry or borrow conditions for unsigned arithmetic

Carry is useful in unsigned calculations.

Question 79. Overflow flag?

  1. A full cache
  2. A DNS lookup failure
  3. Indicates signed arithmetic overflow in relevant operations
  4. A system reboot
Show correct answer and explanation

Correct answer: C. Indicates signed arithmetic overflow in relevant operations

Signed overflow differs from carry.

Question 80. Increment operation?

  1. Squares a value
  2. Divides by two always
  3. Clears all bits
  4. Adds one to a value
Show correct answer and explanation

Correct answer: D. Adds one to a value

Increment increases a value by one.

Question 81. Immediate addressing?

  1. Uses a literal value in an instruction
  2. Only a pointer in memory
  3. Only a network URL
  4. Only the stack top
Show correct answer and explanation

Correct answer: A. Uses a literal value in an instruction

Immediate operands are encoded constants.

Question 82. Register addressing?

  1. Uses a disk block
  2. Uses a CPU register operand
  3. Uses only a memory-mapped device
  4. Uses a domain name
Show correct answer and explanation

Correct answer: B. Uses a CPU register operand

The register provides the operand.

Question 83. Direct addressing?

  1. Always accesses a literal only
  2. Only uses the stack pointer
  3. Specifies a memory address through instruction encoding
  4. Always uses no memory
Show correct answer and explanation

Correct answer: C. Specifies a memory address through instruction encoding

The instruction identifies a memory location.

Question 84. Register-indirect addressing?

  1. Uses an immediate constant as the data only
  2. Reads an opcode as data
  3. Discards the register
  4. Uses an address held in a register
Show correct answer and explanation

Correct answer: D. Uses an address held in a register

A register acts as a pointer.

Question 85. Indexed addressing?

  1. Computes effective address using index-related components
  2. Only updates status flags
  3. Only changes instruction length
  4. Always uses address zero
Show correct answer and explanation

Correct answer: A. Computes effective address using index-related components

Indexed modes support array access.

Question 86. Pointer?

  1. Stores only a floating-point exponent
  2. Stores an address or reference to data
  3. Must equal zero
  4. Only identifies a CPU core
Show correct answer and explanation

Correct answer: B. Stores an address or reference to data

Pointers refer to locations.

Question 87. Array element byte offset?

  1. Always equal to index
  2. Only array capacity
  3. Index multiplied by element size for contiguous fixed-size elements
  4. Only element value
Show correct answer and explanation

Correct answer: C. Index multiplied by element size for contiguous fixed-size elements

Scaled indexing locates array entries.

Question 88. Memory alignment?

  1. Only sorts array values
  2. Only encrypts data
  3. Only selects a stack frame
  4. Places data at suitable address boundaries
Show correct answer and explanation

Correct answer: D. Places data at suitable address boundaries

Alignment may matter for hardware accesses.

Question 89. Memory-mapped I/O?

  1. Device registers appear at designated addresses
  2. Only disk files count as devices
  3. Devices never use registers
  4. Only external URLs access hardware
Show correct answer and explanation

Correct answer: A. Device registers appear at designated addresses

Software accesses mapped device controls.

Question 90. Interrupt?

  1. Only a compile error
  2. Event that redirects execution to a handler
  3. Only a branch prediction
  4. Only a stack overflow
Show correct answer and explanation

Correct answer: B. Event that redirects execution to a handler

Interrupt handling services events.

Question 91. Interrupt service routine?

  1. A source compiler
  2. Only a hardware cable
  3. Code that handles an interrupt
  4. A DNS resolver
Show correct answer and explanation

Correct answer: C. Code that handles an interrupt

An ISR responds to interrupts.

Question 92. Polling?

  1. Always waits for interrupts only
  2. Encrypts every device register
  3. Only allocates RAM
  4. Repeatedly checks device status
Show correct answer and explanation

Correct answer: D. Repeatedly checks device status

Polling examines readiness.

Question 93. DMA?

  1. Direct Memory Access
  2. Dynamic Machine Arithmetic
  3. Data Mapping Array
  4. Digital Memory Algorithm
Show correct answer and explanation

Correct answer: A. Direct Memory Access

DMA performs transfers with limited CPU involvement.

Question 94. Bus bandwidth?

  1. Only number of assembly keywords
  2. Data transfer capacity of an interconnect
  3. Only RAM size
  4. Only number of users
Show correct answer and explanation

Correct answer: B. Data transfer capacity of an interconnect

Bandwidth measures transferable data rate.

Question 95. System bus?

  1. Only a software class
  2. Only a file index
  3. Carries information among hardware components
  4. Only a website
Show correct answer and explanation

Correct answer: C. Carries information among hardware components

Buses convey data addresses or control.

Question 96. Instruction pipelining?

  1. Always performs one instruction at a time without overlap
  2. Eliminates memory
  3. Requires no control logic
  4. Overlaps stages of multiple instructions
Show correct answer and explanation

Correct answer: D. Overlaps stages of multiple instructions

Pipelining improves potential throughput.

Question 97. Data hazard?

  1. Dependence on results of earlier instructions
  2. Only wrong DNS address
  3. Only a disk fault
  4. Only overheating
Show correct answer and explanation

Correct answer: A. Dependence on results of earlier instructions

Dependencies can delay pipelines.

Question 98. Control hazard?

  1. Only register allocation
  2. Uncertain instruction path due to branches
  3. Only cache replacement
  4. Only binary encoding
Show correct answer and explanation

Correct answer: B. Uncertain instruction path due to branches

Branch decisions can change fetch flow.

Question 99. Structural hazard?

  1. Only two variables share a name
  2. Only an invalid opcode
  3. Competing instructions require the same limited resource
  4. Only a stack pop
Show correct answer and explanation

Correct answer: C. Competing instructions require the same limited resource

Resource conflicts cause stalls.

Question 100. Branch prediction?

  1. Ensures every branch correct
  2. Removes jumps
  3. Only encrypts code
  4. Speculatively estimates branch outcome
Show correct answer and explanation

Correct answer: D. Speculatively estimates branch outcome

Prediction keeps pipelines busy.

Computer Organization and Assembly Language MCQs — Questions 101–150

Reveal the answer and explanation after considering each question.

Question 101. CPU instruction-level parallelism?

  1. Independent instructions overlap in execution
  2. Only multiple applications start
  3. Every code line runs twice
  4. CPU frequency doubles
Show correct answer and explanation

Correct answer: A. Independent instructions overlap in execution

ILP exploits independent instructions.

Question 102. Pipeline cycle time primarily depends on?

  1. Shortest stage only
  2. Slowest pipeline stage plus overhead
  3. Total program lines
  4. Disk capacity
Show correct answer and explanation

Correct answer: B. Slowest pipeline stage plus overhead

A stage bottleneck limits clock speed.

Question 103. Ideal 5-stage pipeline first result after?

  1. 1 cycle
  2. 10 cycles
  3. 5 cycles
  4. 2 cycles
Show correct answer and explanation

Correct answer: C. 5 cycles

The first instruction completes all five stages.

Question 104. Ideal 5-stage pipeline completing 10 instructions uses?

  1. 10 cycles
  2. 50 cycles
  3. 5 cycles
  4. 14 cycles
Show correct answer and explanation

Correct answer: D. 14 cycles

Total ideal latency equals 5+10-1 cycles.

Question 105. One-issue ideal pipeline steady throughput?

  1. One instruction per cycle
  2. Five instructions per cycle always
  3. One per five cycles
  4. No completion
Show correct answer and explanation

Correct answer: A. One instruction per cycle

Once full the pipeline can retire one per cycle.

Question 106. Read-after-write hazard?

  1. Two instructions only read a value
  2. A later instruction requires an earlier result
  3. Two instructions write independent registers
  4. A cache miss alone
Show correct answer and explanation

Correct answer: B. A later instruction requires an earlier result

RAW is a true dependency.

Question 107. Write-after-read hazard?

  1. A later read requires an earlier write
  2. Only two reads
  3. A later write may overtake an earlier read
  4. A power failure
Show correct answer and explanation

Correct answer: C. A later write may overtake an earlier read

WAR is an anti-dependency.

Question 108. Write-after-write hazard?

  1. Two separate reads
  2. A page fault
  3. Two branches use the same target
  4. Two writes to one logical destination may be reordered
Show correct answer and explanation

Correct answer: D. Two writes to one logical destination may be reordered

WAW is an output dependency.

Question 109. Register renaming reduces?

  1. False register dependencies
  2. All RAW dependencies
  3. All memory delays
  4. All cache misses
Show correct answer and explanation

Correct answer: A. False register dependencies

Physical register mapping removes WAR and WAW restrictions.

Question 110. Out-of-order execution?

  1. Violates all dependencies
  2. Executes ready instructions around stalled earlier ones
  3. Always changes program meaning
  4. Only reorders files
Show correct answer and explanation

Correct answer: B. Executes ready instructions around stalled earlier ones

Scheduling can improve resource utilization.

Question 111. Instruction retirement in order supports?

  1. Only faster disks
  2. Disabling interrupts
  3. Precise architectural state
  4. Only debugging symbols
Show correct answer and explanation

Correct answer: C. Precise architectural state

Ordered commit maintains exceptions and visible state.

Question 112. Reorder buffer function?

  1. Store website files
  2. Count CPU pins
  3. Assign network ports
  4. Track speculative work for ordered retirement
Show correct answer and explanation

Correct answer: D. Track speculative work for ordered retirement

ROB entries manage instruction completion.

Question 113. Speculative execution?

  1. Run predicted work before outcomes become certain
  2. Always remove branch instructions
  3. Read only ROM
  4. Require no dependencies
Show correct answer and explanation

Correct answer: A. Run predicted work before outcomes become certain

Predicted paths may execute before confirmation.

Question 114. Branch predictor role?

  1. Select CPU voltage alone
  2. Estimate branch direction or target
  3. Create passwords
  4. Encrypt program data
Show correct answer and explanation

Correct answer: B. Estimate branch direction or target

Prediction reduces fetch stalls.

Question 115. Branch misprediction penalty?

  1. All data are lost
  2. RAM capacity doubles
  3. Wrong-path work must be discarded
  4. CPU instructions become longer
Show correct answer and explanation

Correct answer: C. Wrong-path work must be discarded

Incorrect speculation wastes cycles.

Question 116. CPI represents?

  1. Core count per instruction
  2. Cache pages per input
  3. Characters per identifier
  4. Average cycles per retired instruction
Show correct answer and explanation

Correct answer: D. Average cycles per retired instruction

CPI is average clocks per instruction.

Question 117. 2 GHz clock with CPI 2 yields approximately?

  1. 1 billion instructions per second
  2. 2 billion
  3. 4 billion
  4. 500 thousand
Show correct answer and explanation

Correct answer: A. 1 billion instructions per second

2 billion cycles divided by 2 CPI gives 1 billion.

Question 118. IPC denotes?

  1. Interrupts per codeword
  2. Instructions per cycle
  3. Inputs per cache
  4. Indices per core
Show correct answer and explanation

Correct answer: B. Instructions per cycle

IPC measures retired instructions per cycle.

Question 119. CPU execution time formula?

  1. Only RAM size times CPU frequency
  2. Only instruction length
  3. Instruction count times CPI times cycle time
  4. Only file size
Show correct answer and explanation

Correct answer: C. Instruction count times CPI times cycle time

Cycle count is instruction count times CPI.

Question 120. Clock frequency measures?

  1. Instructions per clock always
  2. Cache capacity
  3. Number of ALUs
  4. Clock cycles per second
Show correct answer and explanation

Correct answer: D. Clock cycles per second

Hertz measures cycles each second.

Question 121. Clock speed alone is insufficient because?

  1. Instruction counts and CPI vary
  2. All ISAs are identical
  3. CPI always equals one
  4. Compiler choice is irrelevant
Show correct answer and explanation

Correct answer: A. Instruction counts and CPI vary

Performance depends on more than frequency.

Question 122. Amdahl law describes?

  1. Only cache line placement
  2. Speedup limits from unaccelerated work
  3. Only disk throughput
  4. Only machine code length
Show correct answer and explanation

Correct answer: B. Speedup limits from unaccelerated work

Serial work restricts total acceleration.

Question 123. Half the time improved twofold gives total speedup?

  1. 2
  2. 3
  3. 4/3
  4. 4
Show correct answer and explanation

Correct answer: C. 4/3

New time 0.5+0.25=0.75, inverse 4/3.

Question 124. If 20 percent remains serial maximum speedup?

  1. 10
  2. 20
  3. Infinite
  4. 5
Show correct answer and explanation

Correct answer: D. 5

1 divided by 0.2 equals five.

Question 125. Throughput measures?

  1. Completed work per unit time
  2. Only latency of one request
  3. Only cache hit rate
  4. CPU temperature
Show correct answer and explanation

Correct answer: A. Completed work per unit time

Throughput is a processing rate.

Question 126. SIMD means?

  1. Several instructions on one datum necessarily
  2. One instruction applied to multiple data lanes
  3. Only independent programs
  4. One CPU core only
Show correct answer and explanation

Correct answer: B. One instruction applied to multiple data lanes

SIMD exploits data parallelism.

Question 127. Multicore processor?

  1. Contains only multiple registers
  2. Has no cache
  3. Contains multiple processing cores
  4. Uses only one instruction set word
Show correct answer and explanation

Correct answer: C. Contains multiple processing cores

Different cores execute work concurrently.

Question 128. Simultaneous multithreading?

  1. Runs only one software thread
  2. Guarantees 2x speedup
  3. Disables scheduling
  4. Shares one core among multiple hardware threads
Show correct answer and explanation

Correct answer: D. Shares one core among multiple hardware threads

SMT improves utilization of shared execution units.

Question 129. Race condition?

  1. Outcome depends on unsafe timing of concurrent operations
  2. A cache hit
  3. Arithmetic overflow only
  4. A fast program
Show correct answer and explanation

Correct answer: A. Outcome depends on unsafe timing of concurrent operations

Unsynchronized shared access can change results.

Question 130. Atomic read-modify-write?

  1. All memory accesses are encrypted
  2. An indivisible update relative to relevant observers
  3. Every thread waits forever
  4. Only one CPU exists
Show correct answer and explanation

Correct answer: B. An indivisible update relative to relevant observers

Atomic operations help coordinate threads.

Question 131. Mutex use?

  1. Increase page size
  2. Encrypt memory
  3. Protect critical section with mutual exclusion
  4. Change clock rate
Show correct answer and explanation

Correct answer: C. Protect critical section with mutual exclusion

Only the lock holder enters the protected region.

Question 132. Deadlock scenario?

  1. All threads finish
  2. No shared state exists
  3. Only two arithmetic instructions run
  4. Threads wait cyclically on resources
Show correct answer and explanation

Correct answer: D. Threads wait cyclically on resources

Circular wait can prevent progress.

Question 133. Cache coherence?

  1. Maintain consistent shared-data cache views
  2. Only increase cache size
  3. Encrypt all cache lines
  4. Disable writes
Show correct answer and explanation

Correct answer: A. Maintain consistent shared-data cache views

Coherence protocols coordinate copies.

Question 134. Write-invalidate protocol?

  1. Writes every file to disk
  2. Invalidates competing copies before exclusive modification
  3. Always broadcasts passwords
  4. Removes all caches
Show correct answer and explanation

Correct answer: B. Invalidates competing copies before exclusive modification

Invalidation helps maintain shared memory consistency.

Question 135. False sharing?

  1. Two threads share the same logical variable
  2. A cryptographic collision
  3. Independent variables on one cache line cause coherence traffic
  4. A disk formatting error
Show correct answer and explanation

Correct answer: C. Independent variables on one cache line cause coherence traffic

Cache-line granularity can create unwanted contention.

Question 136. Memory consistency model?

  1. Physical RAM manufacturer
  2. Only register count
  3. A file format
  4. Permitted ordering of shared-memory operations
Show correct answer and explanation

Correct answer: D. Permitted ordering of shared-memory operations

Models define what threads may observe.

Question 137. Memory fence?

  1. Constrains ordering of memory operations
  2. Encrypts stack frames
  3. Updates BIOS
  4. Changes every opcode
Show correct answer and explanation

Correct answer: A. Constrains ordering of memory operations

Fences enforce specified ordering.

Question 138. Context switch?

  1. Convert integer bases
  2. Save one task state and load another
  3. Replace a hardware core
  4. Invalidate every file
Show correct answer and explanation

Correct answer: B. Save one task state and load another

OS switches executing contexts.

Question 139. User mode?

  1. Gives full device access
  2. Means firmware boot only
  3. Restricts application execution privileges
  4. Disables memory protection
Show correct answer and explanation

Correct answer: C. Restricts application execution privileges

Applications generally execute with limited privileges.

Question 140. Kernel mode?

  1. Only reads user files
  2. Means a source programming language
  3. A cache coherence state
  4. Enables privileged operating-system operations
Show correct answer and explanation

Correct answer: D. Enables privileged operating-system operations

Kernel code has elevated hardware control.

Question 141. Load-store architecture?

  1. Arithmetic primarily uses registers with separate memory access instructions
  2. All arithmetic acts directly on disk
  3. All instructions include memory writes
  4. Registers cannot contain data
Show correct answer and explanation

Correct answer: A. Arithmetic primarily uses registers with separate memory access instructions

Load-store designs isolate memory operations.

Question 142. RISC commonly emphasizes?

  1. Only huge microcoded instructions
  2. Relatively simple regular instruction formats and operations
  3. No registers
  4. Only stack instruction sets
Show correct answer and explanation

Correct answer: B. Relatively simple regular instruction formats and operations

RISC conventions facilitate decoding and pipelining.

Question 143. CISC traditionally emphasizes?

  1. Only one instruction
  2. No microarchitecture
  3. A larger range of instruction forms and addressing capabilities
  4. No operand modes
Show correct answer and explanation

Correct answer: C. A larger range of instruction forms and addressing capabilities

CISC denotes complex instruction-set designs.

Question 144. Microcode is?

  1. Only source comments
  2. A network security algorithm
  3. A storage filesystem
  4. Internal control sequences implementing some machine instructions
Show correct answer and explanation

Correct answer: D. Internal control sequences implementing some machine instructions

Microprogrammed control can realize ISA behavior.

Question 145. Microarchitecture describes?

  1. Hardware organization implementing an ISA
  2. Only a user manual
  3. Only the ISA instruction names
  4. Only the compiler language
Show correct answer and explanation

Correct answer: A. Hardware organization implementing an ISA

Different processor designs can implement the same ISA.

Question 146. An exception differs from a typical external interrupt by?

  1. Always being generated by keyboard input
  2. Often being caused synchronously by the executing instruction
  3. Never involving operating-system handling
  4. Always halting the CPU permanently
Show correct answer and explanation

Correct answer: B. Often being caused synchronously by the executing instruction

Exceptions arise from instruction execution conditions.

Question 147. A system call permits?

  1. Unrestricted access to kernel memory
  2. Direct power supply replacement
  3. User software to request kernel services through a controlled interface
  4. Only a compiler warning
Show correct answer and explanation

Correct answer: C. User software to request kernel services through a controlled interface

System calls cross a privilege boundary.

Question 148. Privilege levels protect?

  1. Only printed output
  2. Only program names
  3. Only disk file extensions
  4. Sensitive processor operations and memory resources
Show correct answer and explanation

Correct answer: D. Sensitive processor operations and memory resources

Hardware privilege supports isolation.

Question 149. A timer interrupt is useful for?

  1. Preemptive operating-system scheduling
  2. Directly compiling source code
  3. Always increasing RAM
  4. Storing cache tags
Show correct answer and explanation

Correct answer: A. Preemptive operating-system scheduling

Timers let the OS regain control.

Question 150. A memory protection fault may arise from?

  1. An ordinary cache hit
  2. Access violating a page or segment permission
  3. Successful register write
  4. Valid arithmetic multiplication
Show correct answer and explanation

Correct answer: B. Access violating a page or segment permission

Protection prevents unauthorized memory accesses.

Computer Organization and Assembly Language MCQs — Questions 151–200

Choose the correct option and reveal its explanation.

Question 151. What is an instruction encoding?

  1. Only a source code comment
  2. A hardware cooling profile
  3. Binary representation of an ISA instruction
  4. A disk block address
Show correct answer and explanation

Correct answer: C. Binary representation of an ISA instruction

Machine instructions are encoded as bit fields.

Question 152. A fixed-length instruction format helps?

  1. Guarantee smallest code size
  2. Eliminate all registers
  3. Remove all branches
  4. Simplify instruction fetching and decoding
Show correct answer and explanation

Correct answer: D. Simplify instruction fetching and decoding

Uniform widths simplify boundaries and decode.

Question 153. Variable-length instructions can improve?

  1. Code density for some workloads
  2. Guaranteed constant decoding effort
  3. Elimination of alignment considerations
  4. Removal of memory operands
Show correct answer and explanation

Correct answer: A. Code density for some workloads

Short encodings may save instruction storage.

Question 154. What is an addressing mode?

  1. The CPU brand
  2. A rule describing how an instruction obtains its operand or effective address
  3. A security role
  4. Only a clock frequency
Show correct answer and explanation

Correct answer: B. A rule describing how an instruction obtains its operand or effective address

Addressing modes interpret operand fields.

Question 155. PC-relative addressing computes a target from?

  1. Only the stack base
  2. A disk serial number
  3. Program-counter-related value and signed displacement
  4. Only the source filename
Show correct answer and explanation

Correct answer: C. Program-counter-related value and signed displacement

Relative branches encode displacement from an architectural PC reference.

Question 156. Why is PC-relative addressing useful?

  1. It removes branch prediction
  2. It requires no instructions
  3. It disables relocation
  4. Code can branch using offsets without fixed absolute addresses
Show correct answer and explanation

Correct answer: D. Code can branch using offsets without fixed absolute addresses

Relative addresses aid position-independent control flow.

Question 157. A relocation entry in object code helps?

  1. Adjust address-dependent references during linking or loading
  2. Increase CPU voltage
  3. Encrypt opcodes
  4. Choose the cache victim
Show correct answer and explanation

Correct answer: A. Adjust address-dependent references during linking or loading

Relocation corrects references after placement.

Question 158. A symbol table in an assembler or linker records?

  1. Only user passwords
  2. Names and associated address or binding information
  3. Only runtime cache misses
  4. Only memory refresh rates
Show correct answer and explanation

Correct answer: B. Names and associated address or binding information

Symbols connect names to machine locations.

Question 159. A label in assembly commonly identifies?

  1. A hardware peripheral only
  2. A CPU register in every ISA
  3. An instruction or data location for reference
  4. A network port
Show correct answer and explanation

Correct answer: C. An instruction or data location for reference

Labels make branches and addresses readable.

Question 160. What is a pseudo-instruction?

  1. Always a privileged opcode
  2. A CPU manufacturing command
  3. An illegal instruction only
  4. An assembler-level notation translated into one or more actual machine instructions
Show correct answer and explanation

Correct answer: D. An assembler-level notation translated into one or more actual machine instructions

Assemblers may expand convenient mnemonics.

Question 161. Why do calling conventions matter?

  1. They coordinate register use argument passing and return behavior across procedures
  2. They specify disk rotation
  3. They determine web page color
  4. They replace ISA definitions
Show correct answer and explanation

Correct answer: A. They coordinate register use argument passing and return behavior across procedures

Shared conventions make separately compiled procedures interoperable.

Question 162. What is a callee-saved register?

  1. A register that every call must clear
  2. A register the called procedure must preserve under the ABI when it uses it
  3. A memory-mapped device
  4. Only the return address
Show correct answer and explanation

Correct answer: B. A register the called procedure must preserve under the ABI when it uses it

The callee restores designated registers before returning.

Question 163. What is a caller-saved register?

  1. A register the callee can never change
  2. Only a stack pointer
  3. A register whose value a caller must preserve if needed across a call
  4. A CPU cache line
Show correct answer and explanation

Correct answer: C. A register whose value a caller must preserve if needed across a call

Callers protect values they need afterward.

Question 164. How are many function arguments passed under modern ABIs?

  1. Only via keyboard input
  2. Only through disk files
  3. Only through instruction opcodes
  4. Through designated registers with stack space when needed
Show correct answer and explanation

Correct answer: D. Through designated registers with stack space when needed

Calling conventions define argument locations.

Question 165. What does a stack overflow in recursive calls often indicate?

  1. Excessive stack growth beyond available stack space
  2. A signed integer overflow always
  3. Only a cache miss
  4. A valid return value
Show correct answer and explanation

Correct answer: A. Excessive stack growth beyond available stack space

Deep recursion can exhaust the call stack.

Question 166. Why are stack frames allocated for procedures?

  1. To store network routing tables only
  2. To manage locals saved registers and call-related state
  3. To replace all registers
  4. To encrypt source code
Show correct answer and explanation

Correct answer: B. To manage locals saved registers and call-related state

Frames organize temporary activation storage.

Question 167. What is a leaf function?

  1. A function with no arguments
  2. A function with no return value
  3. A procedure that makes no further procedure calls
  4. Only an interrupt handler
Show correct answer and explanation

Correct answer: C. A procedure that makes no further procedure calls

Leaf procedures invoke no other functions.

Question 168. What is tail-call optimization?

  1. Converting every loop into recursion
  2. Eliminating all functions
  3. Always increasing stack depth
  4. Reusing a call frame when a call occurs in tail position and constraints permit
Show correct answer and explanation

Correct answer: D. Reusing a call frame when a call occurs in tail position and constraints permit

Tail calls may avoid additional stack growth.

Question 169. What is reentrant code?

  1. Code that can safely be entered again before a prior invocation completes under suitable conditions
  2. Code that runs only once
  3. Code without instructions
  4. A function with one local variable
Show correct answer and explanation

Correct answer: A. Code that can safely be entered again before a prior invocation completes under suitable conditions

Reentrancy requires appropriate state management.

Question 170. Why is stack alignment often required by an ABI?

  1. To ensure every function is recursive
  2. To meet operand access and procedure interoperability rules
  3. To eliminate memory errors automatically
  4. Only for screen drawing
Show correct answer and explanation

Correct answer: B. To meet operand access and procedure interoperability rules

Alignment can be required at call boundaries.

Question 171. What is an I/O controller?

  1. A source editor
  2. A data structure for sorting
  3. Hardware coordinating communication with a peripheral
  4. A compiler pass
Show correct answer and explanation

Correct answer: C. Hardware coordinating communication with a peripheral

Controllers manage device signals and data.

Question 172. What is programmed I/O?

  1. Every transfer occurs solely through DMA
  2. Only disk encryption
  3. A wireless network protocol
  4. CPU executes instructions to transfer data with a device
Show correct answer and explanation

Correct answer: D. CPU executes instructions to transfer data with a device

CPU-driven I/O performs the transfers.

Question 173. Why is interrupt-driven I/O useful?

  1. The CPU need not poll continuously for every device event
  2. Interrupts eliminate all latency
  3. It makes devices faster than RAM always
  4. It requires no handlers
Show correct answer and explanation

Correct answer: A. The CPU need not poll continuously for every device event

Devices can signal when attention is needed.

Question 174. How does DMA improve large transfers?

  1. It disables memory
  2. A controller moves blocks between device and memory with less per-byte CPU involvement
  3. It encrypts all files
  4. It replaces physical buses
Show correct answer and explanation

Correct answer: B. A controller moves blocks between device and memory with less per-byte CPU involvement

DMA reduces CPU copying overhead.

Question 175. What is memory-mapped I/O?

  1. A disk is always treated as RAM
  2. All instructions are I/O instructions
  3. Device registers are accessed through assigned address ranges
  4. Only file names identify devices
Show correct answer and explanation

Correct answer: C. Device registers are accessed through assigned address ranges

Address reads and writes may operate hardware registers.

Question 176. What is a solid-state drive based on?

  1. Magnetic rotating platters exclusively
  2. A paper tape
  3. Only volatile CPU registers
  4. Nonvolatile semiconductor storage
Show correct answer and explanation

Correct answer: D. Nonvolatile semiconductor storage

SSDs commonly use flash memory.

Question 177. A hard disk drive stores information on?

  1. Rotating magnetic media
  2. Only SRAM cells
  3. Only processor registers
  4. Optical fiber
Show correct answer and explanation

Correct answer: A. Rotating magnetic media

HDDs use magnetized spinning platters.

Question 178. Seek time for a hard drive is?

  1. Only data transmission time
  2. Time spent positioning the read/write head over a track
  3. Time to compile a driver
  4. Network propagation delay
Show correct answer and explanation

Correct answer: B. Time spent positioning the read/write head over a track

Mechanical head movement contributes to access latency.

Question 179. Rotational latency in a disk is?

  1. Time to install the OS
  2. CPU clock period
  3. Waiting for the desired sector to rotate under the head
  4. RAM refresh time
Show correct answer and explanation

Correct answer: C. Waiting for the desired sector to rotate under the head

Sector position adds rotational waiting.

Question 180. What is storage throughput?

  1. Only the number of files
  2. Only seek time
  3. The number of passwords
  4. Amount of data transferred per unit time
Show correct answer and explanation

Correct answer: D. Amount of data transferred per unit time

Throughput quantifies transfer rate.

Question 181. A memory hierarchy places faster smaller storage generally?

  1. Closer to the CPU than slower larger storage
  2. Always on external disks
  3. Only in the cloud
  4. Only in firmware
Show correct answer and explanation

Correct answer: A. Closer to the CPU than slower larger storage

Registers and caches are near the processor.

Question 182. Why is SRAM often used for CPU caches?

  1. It is always nonvolatile
  2. It offers low-latency access without DRAM-style refresh
  3. It has higher density than DRAM
  4. It requires a spinning disk
Show correct answer and explanation

Correct answer: B. It offers low-latency access without DRAM-style refresh

SRAM trades area and cost for speed.

Question 183. Why is DRAM common in main memory?

  1. It never needs refresh
  2. It is nonvolatile
  3. It offers greater density at comparatively lower cost per bit
  4. It uses mechanical platters
Show correct answer and explanation

Correct answer: C. It offers greater density at comparatively lower cost per bit

DRAM is denser than typical SRAM.

Question 184. What does DRAM refresh do?

  1. Defragment storage
  2. Encrypt memory pages
  3. Increase register count
  4. Restore charge information in storage cells periodically
Show correct answer and explanation

Correct answer: D. Restore charge information in storage cells periodically

Capacitor charge leaks and needs refresh.

Question 185. What is cache miss penalty?

  1. Additional time to obtain data absent from the current cache
  2. Every instruction’s fixed opcode size
  3. The number of clock cores
  4. Only a compilation warning
Show correct answer and explanation

Correct answer: A. Additional time to obtain data absent from the current cache

Miss penalty measures extra access delay.

Question 186. Average memory access time can be approximated as?

  1. Hit rate divided by CPU count
  2. Hit time plus miss rate times miss penalty
  3. Instruction count times power
  4. Disk capacity plus RAM size
Show correct answer and explanation

Correct answer: B. Hit time plus miss rate times miss penalty

The simple AMAT model accounts for misses.

Question 187. If cache hit time is 1 ns miss rate 10 percent and miss penalty 50 ns then AMAT is?

  1. 5 ns
  2. 51 ns
  3. 6 ns
  4. 1.5 ns
Show correct answer and explanation

Correct answer: C. 6 ns

1 plus 0.1 times 50 equals 6 nanoseconds.

Question 188. If a cache has hit rate 95 percent what is its miss rate?

  1. 95 percent
  2. 10 percent
  3. 0 percent
  4. 5 percent
Show correct answer and explanation

Correct answer: D. 5 percent

Miss rate is 100 minus hit percentage.

Question 189. A compulsory cache miss occurs?

  1. When a block is first accessed without previously being in that cache
  2. Only when cache is full
  3. Only because of associativity
  4. Only from branch misprediction
Show correct answer and explanation

Correct answer: A. When a block is first accessed without previously being in that cache

Cold-start misses occur on first reference.

Question 190. A conflict cache miss occurs when?

  1. The first block is ever accessed
  2. Blocks compete for limited placements within a cache set
  3. The CPU lacks an ALU
  4. A disk file is deleted
Show correct answer and explanation

Correct answer: B. Blocks compete for limited placements within a cache set

Set mapping can cause misses even when total cache capacity could hold blocks.

Question 191. What is a capacity miss?

  1. Only initial compulsory access
  2. Only an interrupt
  3. A miss caused by insufficient cache capacity for needed working data
  4. Only a program-counter change
Show correct answer and explanation

Correct answer: C. A miss caused by insufficient cache capacity for needed working data

Working sets exceeding capacity produce capacity misses.

Question 192. A direct-mapped cache with 16 lines uses how many index bits?

  1. 2
  2. 8
  3. 16
  4. 4
Show correct answer and explanation

Correct answer: D. 4

Sixteen possible line indices need log2(16)=4 bits.

Question 193. A 64-byte cache block uses how many byte-offset bits?

  1. 6
  2. 4
  3. 8
  4. 16
Show correct answer and explanation

Correct answer: A. 6

Sixty-four bytes require six bits to select a byte.

Question 194. A two-way set-associative cache permits?

  1. Only one cache line total
  2. Two candidate lines per indexed set
  3. Any line in the entire cache
  4. Four lines per set necessarily
Show correct answer and explanation

Correct answer: B. Two candidate lines per indexed set

Two ways offer two placements within a set.

Question 195. Cache tags are used to?

  1. Store only CPU temperature
  2. Encrypt all addresses
  3. Determine which memory block occupies a selected line
  4. Choose branch direction
Show correct answer and explanation

Correct answer: C. Determine which memory block occupies a selected line

Tags distinguish blocks sharing a set index.

Question 196. Why can buffer overflow attacks threaten programs?

  1. They only increase file size
  2. They always improve performance
  3. They cannot affect control flow
  4. Out-of-bounds writes may corrupt control data and memory
Show correct answer and explanation

Correct answer: D. Out-of-bounds writes may corrupt control data and memory

Memory corruption may enable crashes or control hijacking.

Question 197. What is a stack canary?

  1. A checked sentinel that can detect some stack overwrites
  2. An instruction format
  3. Only a disk encryption key
  4. A program-counter bit
Show correct answer and explanation

Correct answer: A. A checked sentinel that can detect some stack overwrites

Canaries help detect certain overwrites before return.

Question 198. What does NX or DEP protection do?

  1. Makes all data unreadable
  2. Marks selected memory regions non-executable
  3. Encrypts every register
  4. Prevents all security vulnerabilities
Show correct answer and explanation

Correct answer: B. Marks selected memory regions non-executable

Execution permission can block injected code in data pages.

Question 199. What is address-space layout randomization?

  1. Makes instruction order random
  2. Changes the ISA every run
  3. Randomizes positions of memory regions to make addresses less predictable
  4. Removes stack frames
Show correct answer and explanation

Correct answer: C. Randomizes positions of memory regions to make addresses less predictable

ASLR complicates attacks relying on fixed addresses.

Question 200. What is a precise exception?

  1. An exception that never interrupts
  2. A source-code syntax error
  3. An error that only affects graphics
  4. An exception presented with a coherent architectural state at an instruction boundary
Show correct answer and explanation

Correct answer: D. An exception presented with a coherent architectural state at an instruction boundary

Precise exceptions support restart and debugging.

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