Correct answer: A. Both binary inputs are one

An AND gate outputs 1 only when both inputs are 1. Its truth table gives 0 for the input pairs 00, 01, and 10.

Correct answer: B. Both inputs are zero

An OR gate outputs 0 only if both inputs are 0. Any input of 1 makes the two-input OR output 1.

Correct answer: C. 1

XOR outputs 1 when its two inputs differ. Since 1 and 0 are different, 1 XOR 0 = 1.

Correct answer: D. 0

NOT reverses a single binary input: NOT 1 = 0, while NOT 0 = 1.

Correct answer: A. It can implement every Boolean function with suitable connections

NAND is functionally complete: NOT can be formed by joining its inputs, and combinations of NAND gates can implement AND, OR and any Boolean function.

Correct answer: B. Present inputs

A combinational circuit has no stored internal state, so its output is a function of its current inputs. A two-input adder is a common example.

Correct answer: C. Stored state and current inputs

A sequential circuit can depend on the current inputs and stored state from previous clock events. Flip-flops provide the memory.

Correct answer: D. One bit

A flip-flop has two stable states and therefore stores one bit, either 0 or 1. Several flip-flops can form a multibit register.

Correct answer: A. One of several data inputs

A multiplexer uses select inputs to route one of several data inputs to a common output. For example, a 4-to-1 multiplexer typically has two select bits.

Correct answer: B. A coded input to selected outputs

A decoder activates a selected output corresponding to a binary input code. A typical n-to-2^n decoder has 2^n possible outputs.

Correct answer: C. Two input bits without carry-in

A half adder adds two one-bit operands but has no carry-in input. It produces a sum bit and a carry-out bit.

Correct answer: D. Two data bits and a carry-in

A full adder combines two operand bits and an incoming carry. Its outputs are a sum and carry-out, so full adders can be chained.

Correct answer: A. Carry propagation through stages

In a ripple-carry adder each higher bit may have to wait for the carry from a lower stage. Delay increases with the length of the carry chain.

Correct answer: B. Carry computation speed

Carry-lookahead uses generate and propagate information to determine carries without waiting for each stage in sequence. This reduces carry delay.

Correct answer: C. ALUs registers and data routes

The datapath includes registers, arithmetic and logic units, and interconnections used to move and transform data. Control signals decide which operations occur.

Correct answer: D. Signals governing datapath operation

A control unit issues signals such as register enables, ALU operation selects, and memory read/write controls. These coordinate the datapath.

Correct answer: A. A collection of fast registers with access ports

A register file is a collection of relatively fast, directly addressable registers with read and write ports. It holds operands used by CPU instructions.

Correct answer: B. Defined states and transitions

A finite-state controller uses states and transition conditions to sequence machine operations. Each state can specify control outputs for that step.

Correct answer: C. Stored microinstructions

Microprogrammed control stores microinstructions in a control store. A sequencer selects microinstructions whose fields drive lower-level processor operations.

Correct answer: D. Programmer-visible instructions and state

An ISA defines the programmer-visible machine behavior: instructions, register state, data types and addressing semantics. Different microarchitectures may implement the same ISA.

Correct answer: A. The instruction operation

The opcode specifies which operation an instruction performs, such as ADD, LOAD, or BRANCH. Other fields specify operands or modes.

Correct answer: B. A value or location used by an instruction

An operand is a value, register, memory location, or immediate argument used by an instruction. For addition, operands are the values being added.

Correct answer: C. A next instruction address

The program counter usually identifies the address of the next instruction to fetch or execute, depending on architecture and pipeline conventions.

Correct answer: D. A fetched instruction representation

The instruction register holds bits of an instruction fetched from memory. Decoding interprets these fields to determine the required operation.

Correct answer: A. A literal encoded in the instruction

An immediate operand is a literal value embedded in the instruction encoding. It does not require fetching the operand from a separate data-memory location.

Correct answer: B. A register holds an operand’s memory address

In register-indirect addressing, a register contains the address of the memory operand rather than the operand value itself. The processor dereferences that address.

Correct answer: C. Program counter reference plus displacement

PC-relative addressing calculates a target using a displacement relative to a defined program-counter value. It is commonly used for branches.

Correct answer: D. Register operands

In a load-store ISA, arithmetic generally operates on register operands. Dedicated load and store instructions access memory.

Correct answer: A. Bit fields for opcode and operands

An instruction format specifies fields such as opcode, register identifiers, addressing mode and immediate values, together with their bit positions.

Correct answer: B. Regular relatively simple operations

Traditional RISC design emphasizes relatively regular, simple instructions and load/store memory access. Such regularity can simplify instruction decoding and pipelines.

Correct answer: C. Many operations and addressing modes

Historically, CISC ISAs provide varied instruction operations and addressing modes, sometimes combining memory access and computation. Modern implementations may decode them into simpler micro-operations.

Correct answer: D. A hardware design implementing an ISA

Microarchitecture describes how the processor hardware executes a given ISA, including pipelines, caches, execution units and internal control.

Correct answer: A. Binary conventions for calls and data layout

An ABI defines binary-level conventions such as calling sequences, data layout, register preservation and object-file interfaces to support interoperability.

Correct answer: B. Arguments register preservation and return values

A calling convention defines how arguments and return values are passed and which registers each caller or callee must preserve across function calls.

Correct answer: C. Its least significant byte

Little-endian order stores the least significant byte at the lowest address. For example, 0x1234 is stored as bytes 0x34 then 0x12.

Correct answer: D. Its most significant byte

Big-endian order stores the most significant byte at the lowest address. For example, 0x1234 is stored as bytes 0x12 then 0x34.

Correct answer: A. Negative 128 through 127

With 8 bits, two’s complement represents integers from −2^7 to 2^7 − 1, giving −128 through 127.

Correct answer: B. Signed value when increasing width

Sign extension replicates the most significant sign bit when widening a signed two’s-complement integer, preserving its numeric value.

Correct answer: C. Floating-point representations and operations

IEEE 754 specifies widely used floating-point formats, rounding behavior, special values and arithmetic requirements, enabling more consistent numerical computation.

Correct answer: D. Significant precision digits

The significand contains the significant precision bits or digits of a floating-point number. The exponent determines the scale.

Correct answer: A. Cycles per second

Clock frequency counts cycles per second, measured in hertz. A 2 GHz clock provides two billion cycles per second, not necessarily two billion completed instructions.

Correct answer: B. Cycles per instruction on average

CPI is the average number of clock cycles per completed instruction for a measured instruction stream. Workload and architecture can influence CPI.

Correct answer: C. Instructions per clock cycle

IPC is the average number of instructions completed per clock cycle. For the same measurement interval, IPC is approximately the reciprocal of CPI.

Correct answer: D. Instruction count CPI and clock period

CPU time equals instruction count multiplied by average CPI and clock-cycle time. Equivalently, time equals instruction count × CPI divided by frequency.

Correct answer: A. Speedup limited by unaffected work

Amdahl’s law states that speedup of an accelerated portion is limited by the portion that remains unchanged or serial. Even unlimited cores cannot remove serial work.

Correct answer: B. One billion instructions per second

2 GHz means 2 × 10^9 cycles/s. At 2 cycles/instruction, the rate is (2 × 10^9)/2 = 10^9 instructions/s.

Correct answer: C. 5

A strictly serial fraction of 0.20 limits speedup to 1/0.20 = 5 as parallel resources approach infinity, assuming Amdahl’s fixed-workload model.

Correct answer: D. Encoded operation and any associated operand fields

A machine instruction encodes an operation and, when required, fields identifying registers, constants, memory addresses or addressing modes. Formats vary by ISA.

Correct answer: A. A location in an address space

A memory address names a location in an address space. Hardware and memory-management mechanisms translate or interpret it to access storage.

Correct answer: B. Data address or control information between components

A system bus carries data, address and control information between hardware components. Different buses may separate or multiplex these signals.

Correct answer: C. Recent data may be used again soon

Temporal locality means a recently accessed item is likely to be accessed again soon. Keeping such data in a cache can reduce future access time.

Correct answer: D. Nearby addresses are likely to be accessed

Spatial locality means accesses often occur at nearby addresses. Caches exploit this by fetching whole blocks or lines rather than single bytes.

Correct answer: A. The requested block is in cache

A hit occurs when a requested memory block is already present in the relevant cache. The processor can use the faster cache access instead of fetching from the next level.

Correct answer: B. The requested block is absent from cache

A miss occurs when a requested block is not present in the cache. The memory hierarchy must retrieve it from a lower level, adding a miss penalty.

Correct answer: C. A fixed-size cached memory block

A cache line is the unit of data transferred and stored in a cache, commonly a fixed-size block. Adjacent bytes share a line and can exploit spatial locality.

Correct answer: D. One possible line per memory block

Each memory block maps to one predetermined cache line in a direct-mapped cache. This simple organization can suffer conflict misses when blocks compete for that slot.

Correct answer: A. Any eligible line can hold a block

A fully associative cache allows a memory block to occupy any cache line. Tag comparisons and replacement logic are more flexible but often more expensive.

Correct answer: B. Two lines per set

In a two-way set-associative cache, each set has two line slots or ways. A block maps to one set but may occupy either way within it.

Correct answer: C. Identifies which memory block is stored

The tag distinguishes which of the memory blocks mapping to a set currently occupies a particular cache line. A cache hit requires a matching valid tag.

Correct answer: D. 6 bits

With byte addressing, 64 bytes require log2(64) = 6 offset bits. These select an individual byte position within the cache line.

Correct answer: A. 5 index bits

Thirty-two sets require log2(32) = 5 index bits. The index chooses the set to search in a set-associative or direct-mapped cache.

Correct answer: B. First-time access to an uncached block

A compulsory or cold miss occurs on a block’s first access before the block has been brought into the cache. It is not due to eviction of a previously cached block.

Correct answer: C. Mapped blocks compete for limited slots

A conflict miss happens when blocks compete for the same constrained cache placement, even though other cache locations might have been available.

Correct answer: D. Useful data exceed cache size

A capacity miss occurs because the working data exceeds the cache’s ability to retain all needed blocks. Evictions can cause later reaccesses to miss.

Correct answer: A. Least recently accessed line

Least Recently Used (LRU) replaces the line that has not been accessed for the longest time among candidates. Hardware often approximates true LRU for larger sets.

Correct answer: B. Propagates stores to lower memory as part of the write

A write-through policy forwards each cache write to the next storage level as part of the write operation, often using a buffer. This keeps the lower level more up to date.

Correct answer: C. Allows delayed lower-level writes

A write-back cache marks modified lines dirty and defers lower-level updates until eviction or another required event. It reduces repeated memory traffic for frequently written data.

Correct answer: D. Marks data modified relative to backing storage

A dirty bit shows that a cached line differs from the corresponding lower-level copy. Such a line normally needs writing back before it can be discarded.

Correct answer: A. Allocates a line on a store miss

Under write allocate, a store miss causes the missing block to be loaded or allocated in the cache before or as the store is handled. No-write-allocate is an alternative.

Correct answer: B. Hit time plus miss rate times miss penalty

The basic formula is AMAT = hit time + miss rate × miss penalty. It assumes a simple cache model with one relevant miss-penalty term.

Correct answer: C. 6 ns

AMAT = 2 ns + 0.10 × 40 ns = 6 ns. The miss contribution is 4 ns on average, added to the hit-access time.

Correct answer: D. Often reduces accesses to slower levels

A higher hit rate usually reduces accesses to slower memory levels. Actual performance also depends on cache hit time and the cost of remaining misses.

Correct answer: A. Processor caches

Static RAM is widely used for processor caches because it offers fast access without periodic refresh. Its lower density makes it more expensive per bit than DRAM.

Correct answer: B. Main system memory

Dynamic RAM is commonly used for main memory because it provides high storage density at a lower cost per bit. It is slower than on-chip SRAM caches.

Correct answer: C. Restores leaking charge in cells

DRAM stores information as charge that leaks over time. Refresh operations restore the charge before stored bits become unreliable.

Correct answer: D. Provides address-space protection and abstraction

Virtual memory gives programs virtual address spaces and supports translation, isolation and protection. It can also allow pages to be backed by storage when needed.

Correct answer: A. Records mappings and permissions

Page tables associate virtual pages with physical frames and track control information such as permissions and validity. They are consulted during address translation.

Correct answer: B. Recent address translations

A TLB caches recent virtual-to-physical translations, often including access permissions. This avoids a page-table walk on many memory accesses.

Correct answer: C. Requires finding a translation elsewhere

A TLB miss requires obtaining the translation from another source, commonly by walking page tables. A TLB miss does not necessarily imply the requested page is absent from RAM.

Correct answer: D. Causes memory-management fault handling

A page fault invokes the operating system’s fault handler for a missing, protected or otherwise invalid mapping. It may load a page or terminate an invalid access.

Correct answer: A. Stays unchanged in ordinary page translation

The offset within the page stays unchanged because virtual pages map to physical frames of the same size. Translation replaces the page number, not the in-page position.

Correct answer: B. 12 bits

Four kibibytes equal 4096 = 2^12 bytes. With byte addressing, 12 bits specify the offset within one page.

Correct answer: C. Increase TLB reach per entry

A larger page maps more bytes per TLB entry, increasing TLB reach. The tradeoffs include possible internal fragmentation and less flexible fine-grained protection.

Correct answer: D. Chooses a victim resident page

Page replacement chooses a resident page to evict when a frame is needed. The policy aims to limit future faults while respecting dirty-page write costs.

Correct answer: A. Recently accessed pages

The working set is the set of pages referenced over a recent window of execution. Its size approximates the memory the process currently needs for efficient progress.

Correct answer: B. Excessive paging reduces useful work

Thrashing occurs when the system spends excessive time handling page faults and moving pages instead of doing useful computation. Insufficient physical memory is a common cause.

Correct answer: C. Overlaps instruction processing stages

Pipelining divides instruction execution into stages and overlaps different instructions across stages. It improves potential throughput even if individual latency is not reduced.

Correct answer: D. 14 cycles

With five stages, the first instruction completes after five cycles. Nine additional instructions each complete one cycle later: 5 + 10 − 1 = 14 cycles, assuming no stalls.

Correct answer: A. An instruction depends on another’s result

A data hazard occurs when instruction operands depend on values not yet available from earlier operations. Forwarding or stalling can resolve the timing conflict.

Correct answer: B. Unknown next fetch path after a branch

A control hazard occurs when the next instruction address depends on an unresolved branch or other control transfer. Prediction reduces the resulting fetch delay.

Correct answer: C. Multiple instructions contend for unavailable hardware

A structural hazard occurs when concurrent instructions need the same hardware resource and there are insufficient units or ports to serve them together.

Correct answer: D. Feeds a result to its consumer before register writeback

Forwarding passes a produced result directly from an execution stage to a dependent stage before it is written into the architectural register file.

Correct answer: A. A stage slot without useful progressing instruction

A bubble is an unoccupied or nonproductive pipeline slot, often introduced by a stall. Bubbles lower the achieved instruction throughput.

Correct answer: B. Estimates branch outcome or target early

Branch prediction estimates branch direction and possibly target early, allowing instruction fetching to continue while the branch outcome is unresolved.

Correct answer: C. A dependent operation needs load data before it is ready

A load-use hazard happens when the result of a load has not arrived by the time a dependent instruction needs it. Some pipelines must insert stalls.

Correct answer: D. Discards wrong-path speculative work

A misprediction causes wrong-path speculative instructions to be discarded or squashed and fetching to restart at the correct target, wasting pipeline work.

Correct answer: A. Completed instructions per unit time

Throughput is the number of instructions completed per unit time, such as instructions per cycle or per second. It differs from latency of one instruction.

Correct answer: B. Up to one instruction per cycle after filling

An ideal single-issue pipeline completes at most one instruction per cycle after filling, assuming sufficient instruction supply and no stalls.

Correct answer: C. Can limit clock improvement from additional stages

Each additional pipeline boundary requires registers and control overhead. Very short stages may no longer overcome these costs or other circuit delays.

Correct answer: D. Makes stage delays more similar to reduce bottleneck effects

The cycle period is usually constrained by the slowest stage plus register overhead. Making stage delays more equal can improve achievable clock frequency.

Correct answer: A. Can issue multiple instructions per cycle when dependencies and resources permit

A superscalar CPU can issue more than one instruction per cycle when dependencies and execution resources permit. Multiple pipelines exploit instruction-level parallelism.

Correct answer: B. Independent instructions can execute concurrently

ILP is the opportunity to execute independent instructions from one instruction stream at the same time. Data and control dependencies limit available ILP.

Correct answer: C. Chooses ready operations at runtime using hardware scheduling

Dynamic scheduling selects operations that are ready during execution instead of relying entirely on static program order. Hardware can react to cache misses and variable latency.

Correct answer: D. Executes ready younger instructions before some older stalled operations

Out-of-order processors can execute a younger ready instruction while an older instruction waits for an operand. They usually preserve required architectural behavior at retirement.

Correct answer: A. Makes architectural results visible in program order

In-order retirement commits results in program order, helping preserve precise architectural state and exception behavior even when execution was speculative or out of order.

Correct answer: B. Later instruction reads a value produced by an earlier instruction

RAW is a true data dependency: a later instruction needs a value written by an earlier instruction. It cannot be removed simply by assigning different register names.

Correct answer: C. A younger write must not precede an older read of the same logical location

WAR is an anti-dependency: a later write must not overwrite a name before an earlier instruction has read its value. Register renaming can remove this naming hazard.

Correct answer: D. Writes to the same destination must preserve required ordering

WAW is an output dependency: two writes use the same architectural destination, so their visible order matters. Renaming can give the versions separate physical locations.

Correct answer: A. False register-name dependencies

Renaming removes many false name dependencies, especially WAR and WAW, by assigning different physical registers to successive logical register versions.

Correct answer: B. Store separately versioned values mapped from architectural registers

Physical registers hold actual value versions while a rename map associates architectural registers with their current physical locations. This enables overlap of independent operations.

Correct answer: C. Hold instructions waiting for operands or execution resources

A reservation station holds an issued instruction until its operands and a suitable execution unit are ready. It supports scheduling based on operand availability.

Correct answer: D. Tracks speculative instructions to support ordered commit

A reorder buffer tracks in-flight instructions and their completion status so results can retire in order. It supports precise exceptions and recovery from speculation.

Correct answer: A. Performs work before some control outcomes are confirmed

Speculative execution performs work before a branch or other dependency is resolved. Incorrectly speculated results must be squashed rather than committed.

Correct answer: B. Caches likely branch destination addresses

A BTB caches predicted target addresses of branches or jumps. It helps the fetch unit begin reading the likely destination without waiting for target computation.

Correct answer: C. Uses four prediction states with hysteresis

A two-bit counter has four states and typically requires two contradictory outcomes to switch a strong prediction. This hysteresis avoids overreacting to one unusual branch.

Correct answer: D. Flushing or squashing incorrect speculative instructions

After a wrong prediction, the CPU must discard wrong-path instructions and restart fetching from the actual destination. The lost work is a misprediction penalty.

Correct answer: A. Reports a fault with coherent architectural state at a clear instruction boundary

A precise exception presents architectural state as if all earlier instructions completed and later instructions had no visible effects. It eases restart and debugging.

Correct answer: B. Temporarily holds pending stores

A store buffer holds pending writes until the memory subsystem can accept them. It permits a processor to continue without blocking on every individual store.

Correct answer: C. Tracks memory instructions and their ordering dependencies

A load-store queue tracks memory operations, addresses and ordering constraints. It can detect conflicting speculative loads and stores that require replay.

Correct answer: D. Predicts whether a load may safely proceed before older stores are fully resolved

Memory-dependence speculation predicts whether a load can execute before older stores are fully resolved. An unexpected address overlap may require the load to replay.

Correct answer: A. Uses long instruction words encoding multiple operations scheduled largely by software

VLIW encodes multiple operations within one long instruction word, with operation scheduling largely determined by the compiler. Hardware may be simpler but timing assumptions matter.

Correct answer: B. Compiler knowledge of operation dependencies

VLIW compilers need knowledge of instruction dependencies, operation latencies and functional-unit availability to fill parallel issue slots safely.

Correct answer: C. Runtime latency variations can invalidate static timing assumptions

Static VLIW schedules may perform poorly when runtime delays vary, for example due to unpredictable cache misses. The hardware often has less freedom to reschedule dynamically.

Correct answer: D. Overlaps operations from different loop iterations

Software pipelining overlaps operations from different loop iterations. It constructs a repeating schedule that keeps hardware units busy after startup.

Correct answer: A. Replicates loop body work to reduce overhead or expose parallelism

Loop unrolling duplicates the body of several iterations. This reduces branch overhead and can expose more independent instructions, at the cost of code size.

Correct answer: B. One instruction operates on multiple data elements

SIMD performs one instruction on several data elements simultaneously. It is most effective when many lanes can execute the same operation.

Correct answer: C. Number of elements processed by a vector operation or register under its model

Vector length is the number of elements handled by a vector instruction or register under the relevant ISA. Some architectures support variable vector lengths.

Correct answer: D. A parallel element-processing portion of vector hardware

A SIMD lane is a hardware path that processes one or more elements of a vector operation. Many lanes increase throughput for independent data.

Correct answer: A. Independent repetitive operations over data arrays

Independent element-wise operations on arrays are ideal candidates for vectorization. Loop-carried dependencies and irregular branching can limit benefits.

Correct answer: B. Conditionally activates selected vector elements

An execution mask activates only selected vector elements for a particular operation. Masking handles conditional work without necessarily branching all lanes.

Correct answer: C. Contains multiple independent processing cores

A multicore CPU integrates multiple processing cores that can run different instruction streams. The cores may share some caches and memory interfaces.

Correct answer: D. Presents several hardware thread contexts on a core

SMT lets more than one hardware thread context share a physical core’s execution resources. It can make use of otherwise idle functional units.

Correct answer: A. Can switch active hardware thread between short intervals such as cycles

Fine-grained multithreading switches among hardware thread contexts at short intervals, sometimes each cycle. It can hide latency by interleaving work.

Correct answer: B. Switches threads on larger latency events under a defined design

Coarse-grained multithreading switches contexts less frequently, such as when an extended stall occurs. This reduces switching frequency but may leave some short stalls exposed.

Correct answer: C. Concurrent execution of distinct instruction streams

Thread-level parallelism arises when separate threads execute independent or coordinated streams concurrently, potentially on different cores.

Correct answer: D. Cores communicate through a shared address space

Shared-memory processors communicate through loads and stores to a common address space. Synchronization and coherence mechanisms coordinate access.

Correct answer: A. Coordinates copies of shared locations across caches

Coherence keeps cached copies of a memory location appropriately coordinated when processors read and write it. It is distinct from ordering guarantees for different locations.

Correct answer: B. Modified Exclusive Shared Invalid

MESI consists of Modified, Exclusive, Shared and Invalid states. These indicate a cache line’s ownership, sharing and freshness status.

Correct answer: C. A cache has the only up-to-date dirty copy

Modified means the cache holds a dirty, typically exclusive up-to-date copy. The altered data must eventually be propagated to the memory hierarchy.

Correct answer: D. The line cannot supply valid data

An Invalid line cannot be used to satisfy a read because its data are not valid for the current coherence state. It must be refetched or reacquired.

Correct answer: A. Invalidates other cached copies before exclusive write permission

Write-invalidate protocols obtain exclusive write permission and invalidate competing copies before modifying the cache line. Other caches must refetch to observe later updates.

Correct answer: B. Separate variables sharing a coherence line create unnecessary traffic

False sharing happens when threads modify separate variables that occupy the same coherence line. Repeated invalidations can harm performance even without logical data sharing.

Correct answer: C. Defines permitted observation order of memory operations

A memory consistency model specifies which orders of memory operations may be observed by different processors or threads. Programs must use synchronization accordingly.

Correct answer: D. Constrains reordering or visibility of memory operations as specified

A fence restricts reordering or visibility of memory operations under the architecture’s memory model. It is useful for establishing specific synchronization order.

Correct answer: A. Combines reading and updating a location indivisibly under its atomic semantics

An atomic read-modify-write operation reads a value and updates it indivisibly under its atomic semantics. It supports counters, locks and other coordination primitives.

Correct answer: B. Atomically compares a memory value and conditionally replaces it

CAS compares a location with an expected value and writes a replacement only if the comparison succeeds, atomically. This supports many nonblocking algorithms.

Correct answer: C. Grants exclusive access to a critical section

A mutex permits only one holder to enter a protected critical section at a time. Programs must use it consistently around shared mutable state.

Correct answer: D. Results depend on uncontrolled ordering of concurrent actions

A race condition occurs when the outcome of an operation depends on uncontrolled timing of concurrent actions. Synchronization can remove unwanted races.

Correct answer: A. Circular waits for resources held by others

Deadlock can arise when participants each hold resources needed by others and wait indefinitely in a cycle. Resource-ordering disciplines can help prevent it.

Correct answer: B. Records selected microarchitectural events

Hardware performance counters record events such as CPU cycles, cache misses or branch mispredictions. Profiling tools use these values to locate bottlenecks.

Correct answer: C. Memory access latency depends on which node holds the data

Nonuniform Memory Access means that access time varies with memory location relative to the requesting processor. Local memory is usually faster than memory attached to another NUMA node.

Correct answer: D. Placing threads near the memory they frequently use

Keeping frequently accessed data near the cores that use it reduces remote memory traffic. Thread placement and memory allocation policies therefore affect NUMA performance.

Correct answer: A. Maintains shared-memory coherence across its nodes

Cache-coherent NUMA provides a shared address space while coordinating cached copies across nodes. Access times can still differ according to physical location.

Correct answer: B. Tracks sharers or ownership information to coordinate cache-line access

A coherence directory records which caches hold or own a line. Directory messages coordinate invalidation and data transfer without broadcasting every request system-wide.

Correct answer: C. Observes relevant shared interconnect transactions for coherence events

Snooping caches monitor a shared interconnect or suitable broadcast mechanism for transactions relevant to their cache lines. They change states to maintain coherence.

Correct answer: D. Appropriate consistency for writes to individual shared memory locations

Coherence coordinates the values observed for a given shared memory location, including writes and invalidation of stale copies. It does not alone define all ordering between different locations.

Correct answer: A. Processors may reorder memory effects within permitted consistency rules

Modern processors may reorder or delay memory effects within the architecture’s consistency rules. A fence establishes specified ordering needed by synchronization algorithms.

Correct answer: B. Comes from independent writes sharing one coherence granule

Two independent variables may occupy one cache line. Writes by different cores then repeatedly invalidate that same line, causing unnecessary coherence traffic.

Correct answer: C. Binds threads to specified processors or processor sets

Thread pinning restricts a worker to selected CPUs or cores. It can improve cache reuse and memory locality but may reduce scheduling flexibility.

Correct answer: D. Idle workers take tasks from other workers’ queues

An idle worker can steal queued work from a busy worker. This distributes irregular tasks more evenly and reduces idle processor time.

Correct answer: A. Groups threads executing a common instruction stream with masks for divergence

SIMT groups hardware threads that execute a shared instruction stream while individual lanes may be masked. Divergent control flow can require separate masked paths.

Correct answer: B. A hardware-scheduled group of execution lanes or threads

A warp or wavefront is a hardware-scheduled group of GPU lanes or threads. Its exact width and execution rules depend on the GPU architecture.

Correct answer: C. Different threads in a group follow different control paths

Divergence occurs when threads in the same execution group follow different branches. Executing the different paths can reduce effective lane utilization.

Correct answer: D. Combines nearby lane accesses into efficient memory transactions

Coalescing combines compatible memory requests from neighboring lanes into efficient memory transactions. Nearby aligned accesses often use bandwidth better.

Correct answer: A. The fraction or number of resident warps or threads relative to architectural limits

Occupancy describes active or resident warps or threads relative to a GPU’s capacity. It helps hide latency, but the highest occupancy does not always maximize speed.

Correct answer: B. Uses different kinds of processors or accelerators

Heterogeneous systems combine devices with differing strengths, such as CPUs, GPUs and specialized accelerators. Work is assigned according to device capabilities.

Correct answer: C. Matrix-like multiply-accumulate workloads

Tensor accelerators are optimized for matrix-like multiply-accumulate calculations common in machine learning and numerical linear algebra. Supported precision formats affect results.

Correct answer: D. Operations performed per byte of data movement

Arithmetic intensity compares arithmetic work with transferred data, often operations per byte. Higher intensity can make a workload limited by computation rather than memory bandwidth.

Correct answer: A. Compute peak memory bandwidth and arithmetic intensity

The roofline model relates arithmetic intensity, peak arithmetic throughput and memory bandwidth. Its upper performance bound is the lower of compute peak and bandwidth times intensity.

Correct answer: B. Is limited mainly by data movement or memory service capacity

A memory-bound workload is limited primarily by moving or accessing data. Reducing memory traffic or improving locality can help more than increasing arithmetic units.

Correct answer: C. Is limited mainly by arithmetic execution capability

A compute-bound workload is limited mainly by arithmetic execution throughput. Improvements to vectorization or compute-unit utilization may raise performance.

Correct answer: D. Time for an individual operation to complete

Latency measures elapsed time from an operation’s initiation to completion. A system can have high throughput even when individual operations have relatively high latency.

Correct answer: A. Completed work per unit time

Throughput measures completed work per unit time, such as instructions per second or bytes per second. It describes capacity rather than the delay of one request.

Correct answer: B. Old execution time divided by new execution time

Speedup is old execution time divided by new execution time for the same workload. For example, reducing runtime from 12 s to 4 s gives speedup 3.

Correct answer: C. Useful work per joule

One energy-efficiency metric is useful completed work per joule. Energy efficiency must consider both power use and the amount of useful work performed.

Correct answer: D. Switching activity capacitance voltage squared and frequency

Dynamic CMOS power is approximately proportional to switching activity × effective capacitance × voltage squared × clock frequency: P ≈ αCV²f.

Correct answer: A. Dynamic switching energy

Charging and discharging capacitance consumes energy proportional to voltage squared. Lower voltage therefore reduces dynamic energy, though frequency and reliability constraints matter.

Correct answer: B. Dynamic power in inactive clocked regions

Clock gating stops unnecessary clock transitions in inactive sequential circuits. Because clock networks can switch frequently, gating can reduce dynamic power.

Correct answer: C. Leakage power in inactive blocks

Power gating disconnects inactive circuitry from its supply to reduce leakage power. Waking a gated block can require time and energy.

Correct answer: D. Hardware reduces operating rate to manage temperature or power limits

Thermal management may lower clock frequency or voltage when temperature or power limits are reached. This protects hardware at the cost of temporary performance.

Correct answer: A. A shared communication pathway among hardware components

A bus is a communication channel shared by system components for data, address or control information. Arbitration may be needed if several devices request access.

Correct answer: B. Provides multiple switchable paths between sources and destinations

A crossbar provides switchable routes between inputs and outputs. It can support concurrent transfers to different destinations, subject to its ports and switching resources.

Correct answer: C. Connects on-chip cores and components using packet or routed links

A network-on-chip uses routed interconnects to connect cores, caches and other on-chip blocks. Packet or flit-based transfers can scale better than one shared bus.

Correct answer: D. Measures transfer capacity across a division of the interconnect

Bisection bandwidth measures the communication capacity across a partition dividing the interconnect into two parts. It helps characterize network throughput under distributed traffic.

Correct answer: A. Connects components in a cycle of links

A ring topology joins components in a cycle. Messages follow one or more ring directions and may need multiple hops to reach their destination.

Correct answer: B. High-speed peripheral interconnection

PCI Express is a high-speed serial expansion interconnect used for devices such as network cards, storage controllers and GPU accelerators.

Correct answer: C. Devices or controllers to transfer memory data with reduced per-byte CPU intervention

DMA allows a device or DMA engine to transfer blocks of data between device buffers and memory without requiring the CPU to copy every byte.

Correct answer: D. Address translation and isolation for device memory access

An IOMMU translates and controls device-accessible addresses. It provides isolation against unauthorized DMA access and supports virtualized I/O.

Correct answer: A. An event requesting processor attention and handler execution

An interrupt requests attention from a processor, often indicating a device event or fault. The processor can suspend normal execution and invoke an appropriate handler.

Correct answer: B. Repeatedly checking device status in software

Polling repeatedly reads a device’s status to determine whether it is ready or has completed work. It avoids some interrupt overhead but can waste CPU cycles.

Correct answer: C. Detecting and correcting specified memory bit errors

Error-correcting codes can detect and correct supported bit-error patterns in memory, such as common single-bit errors, depending on the ECC scheme.

Correct answer: D. Some bit-error patterns such as a single-bit flip

A parity bit changes when an odd number of protected bits flip. Thus simple parity detects single-bit errors but may miss an even number of flips.

Correct answer: A. Detects missed progress and can trigger recovery actions

A watchdog timer detects a missing expected progress signal and can initiate recovery, such as resetting a hung subsystem.

Correct answer: B. Availability under certain drive failures

Mirroring keeps copies of data on separate drives so service may survive a supported drive failure. Mirroring does not protect against all simultaneous failures or logical corruption.

Correct answer: C. Deletion corruption and ransomware can affect mirrored data

Accidental deletion, malware, corruption or ransomware can affect all mirrored copies. Independent versioned backups provide recovery points for logical data loss.

Correct answer: D. Measures a workload under controlled conditions

A benchmark measures performance on a specified workload under stated conditions. Results are meaningful only when workload, hardware and measurement method are relevant.

Correct answer: A. 4

With serial fraction f = 0.25, Amdahl’s limit as parallel resources approach infinity is 1/f = 4. The serial part remains unaccelerated.

Correct answer: B. Scaled workload speedup with increasing processor resources

Gustafson’s law considers increasing problem size as more processors are added. Scaled speedup can grow even when fixed-workload speedup is limited by Amdahl’s law.

Correct answer: C. A resource or coordination limit preventing further performance growth

A bottleneck is a resource or coordination constraint that limits the gain from adding more capacity elsewhere. Memory bandwidth or synchronization can be limiting factors.

Correct answer: D. Appropriate compute memory and interconnect resources for its target workload

A balanced architecture allocates suitable processing, memory and interconnect resources to match its target workloads. Improving just one component may have little overall benefit.